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The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significan...
Accurate modeling of high speed RLC interconnects has become a necessity to address signal integrity issues in current VLSI design. To accurately model a dispersive system of interconnects at highe...
Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The ...
The application of quantum tunnelling devices for high-performance digital circuitry is presented. The reliability of devices based on III/V semiconductor heterostructures is demonstrated and the appl...
In this paper, the intrinsic disadvantages of the nowadays low-cost deep-submicron digital CMOS technologies in respect of the design of high-speed optical communication (OC) systems front-end integr...
We report on the development of evanescently coupled waveguide integrated photodetectors in single-ended,differential and balanced configurations, using a flexible monolithic integration scheme on InP...
Buried tunnel junction vertical-cavity surface-emitting lasers (BTJ-VCSELs) for 1.55 μm wavelength, 3dB-cut-off-frequencies around 8 GHz, modulation bandwidths up to 10 Gbit/s and excellent stationary...
The dispersion compensation research includes mainly the following technologies: negative dispersion fiber, chirped fiber grating, prechirped technique, dispersion-supporting transmission, frequency s...
This paper presents HIBTRA (High Speed Bipolar Transistor Analysis), a high speed non-linear bipolar transistor circuit simulation package. The paper discusses about the modelling of Bipolar Junction ...
The electrical and optical characteristics of the new high-speed Al/a-Si/c-Si(p)/c-Si(n+)/Al and Al/a- SiC/c-Si(p)/c-Si(n+)/Al optically controlled switches are presented in this paper. These switches...
Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection architectures are presented with emphasis given to the dependence of crosstalk and sig...
A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to...
Many recommendations have been made on the proper operating conditions for the laser trimming process. In general these recommendations have centered on accuracy, precision or throughput. In some inst...

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