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In this paper, we present an optimized FPGA implementation of a novel, fast and highly parallelized NTT-based polynomial multiplier architecture, which proves to be effective as an accelerator for lat...
In this paper, we continue the study of bit-parallel multiplier using a nn-term Karatsuba algorithm (KA), recently introduced by Li et al. (IEEE Access 2018). Such a nn-term KA is a generalization of ...
We show that such a type of trinomial combined with the nn-term KA can fully exploit the spatial correlation of entries in related Mastrovito product matrices and lead to a low complexity architecture...
In this paper, we present a low complexity bit-parallel Montgomery multiplier for GF(2m)GF(2m) generated with a special class of irreducible pentanomials xm+xm−1+xk+x+1xm+xm−1+xk+x+1. Base...
We present a Matrix-vector form of Karatsuba multiplication over GF(2m)GF(2m) generated by an irreducible trinomial. Based on shifted polynomial basis (SPB), two Mastrovito matrices for different Kara...
Many lattice based cryptosystems are based on the Ring learning with errors (Ring-LWE) problem. The most critical and computationally intensive operation of these Ring-LWE based cryptosystems is polyn...
In this paper, a new bit-parallel Montgomery multiplier for GF(2m) is presented, where the field is generated with an irreducible trinomial. We first present a slightly generalized version of a newly...
Horizontal collision correlation analysis (HCCA) imposes a serious threat to simple power analysis resistant elliptic curve cryptosystems involving unified algorithms, for e.g. Edward curve unified fo...
A fully homomorphic encryption (FHE) scheme is envisioned as being a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrarily evaluation of a ciph...
This paper is devoted to the design of a 258- bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field progra...
The availability of a new carry-less multiplication instruction in the latest Intel desktop processors significantly accelerates multiplication in binary fields and hence presents the opportunity for ...
We present a subquadratic ternary field multiplier based on the combination of several variants of the Karatsuba-Ofman scheme recently published. Since one of the most relevant applications for this...
A new GF(2n) redundant representation is presented. Squaring in the representation is almost cost-free. Based on the representation, two multipliers are proposed. The XOR gate complexity of the fir...

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